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_______________general description the MAX3761/max3762 limiting amplifiers, with 4mv sensitivity and pecl data outputs, are optimized for operation in low-cost, 622mbps, lan/atm lan fiber optics applications. an integrated power detector senses the input signal? amplitude. a received-signal-strength indicator (rssi) gives an analog indication of the power level, while the complementary loss-of-signal (los) outputs indicate if the input power level exceeds the programmed threshold level. the los threshold can be adjusted to detect signal amplitudes between 3mvp-p and 100mvp-p, providing a 15db los adjustment in fiber optic receivers. the los outputs have 3.5db of hysteresis, which prevents chatter when input signal levels are small. the MAX3761? los outputs are com- patible with ttl-logic levels. the max3762 has pecl los outputs. disable and los can be used to implement a squelch function, which turns off the data outputs when the input signal is below the programmed threshold. ________________________applications 622mbps lan/atm lan receivers 155mbps lan/atm lan receivers ____________________________features chatter-free power detector with programmable loss-of-signal outputs 4mv input sensitivity (pecl loss-of-signal interface logic?ax3766 pecl data outputs single 5v power supply 250ps output edge speed low 15ps pulse-width distortion ttl loss-of-signal interface logic?ax3761 MAX3761/max3762 low-power, 622mbps limiting amplifiers with chatter-free power detect for lans ________________________________________________________________ maxim integrated products 1 czn out+ out- los- los+ disable sub gnd gndo 100pf 50 ? czp r1 100k r2 22k +v cc vth inv MAX3761 c az 150pf 50 ? v cc - 2v v cc en rssi vcco vin+ 10nf 100pf bypass supply c in 5.6nf c in 5.6nf +5v vin- filter c filter _________typical operating circuits 19-1097; rev 2; 8/01 part MAX3761 eep MAX3761c/d max3762 eep -40? to +85? -40? to +85? -40? to +85? temp. range pin-package 20 qsop dice* 20 qsop evaluation kit available ______________ordering information * dice are designed to operate from -40? to +85?, but are tested and guaranteed only at t a = +25?. for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. max3762c/d -40? to +85? dice* __________________pin configuration 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 disable los+ los- v cc v cc en rssi filter top view vcco out+ out- gndo sub gnd vin- vin+ 12 11 9 10 vth inv czn czp qsop MAX3761 max3762 max3762 at end of data sheet.
MAX3761/max3762 low-power, 622mbps limiting amplifiers with chatter-free power detect for lans 2 _______________________________________________________________________________________ absolute maximum ratings dc electrical characteristics (v cc = +4.5v to +5.5v, disable = low, t a = -40? to +85?, unless otherwise noted. typical values are at v cc = +5.0v, t a = +25?.) (note 1) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note 1: dice are tested at t a = +25?. note 2: outputs terminated with 50 ? to v cc - 2v. note 3: voltage measurements are relative to v cc . v cc , vcco............................................................-0.5v to +7.0v filter, rssi, en, vin+, vin-, czp, czn, disable, los+, los-, inv, vth...............-0.5v to (v cc + 0.5v) pecl output current (out+, out-, los+, los-) ............50ma continuous power dissipation (t a = +85?) qsop (derate 9.1mw/? above +85?) .......................591mw operating junction temperature range ...........-40? to +150? processing temperature (die) .........................................+400? storage temperature range .............................-65? to +160? lead temperature (soldering, 10sec) .............................+300? max3762, i vcc MAX3761, i vcc disable = high disable = high MAX3761 MAX3761 (notes 2, 3) (notes 2, 3) logic high max3762 (notes 2, 3) MAX3761 MAX3761 max3762 (note 3) max3762 (notes 2, 3) max3762 (note 3) conditions v v cc - 0.7 v cc -1.2 disabled common-mode output mv -100 100 disabled differential output mv -1830 -1555 pecl data output voltage low (v ol ) mv -1150 -880 pecl data output voltage high (v oh ) mv -1470 disable input pecl low mv -1160 disable input pecl high ma 30 46 25 37 power-supply current v 0.8 disable input low v 2.65 disable input high ? 100 disable input current mv -1830 -1555 los output pecl low v 2.8 los output ttl high v 0.40 los output ttl low mv -1150 -880 los output pecl high units min typ max parameter (t a = +25? to +85?) (t a = -40? to +25?) 0.44
MAX3761/max3762 low-power, 622mbps limiting amplifiers with chatter-free power detect for lans _______________________________________________________________________________________ 3 ac electrical characteristics (v cc = +4.5v to +5.5v, pecl outputs terminated with 50 ? to v cc - 2v, input 4mv to 2vp-p, t a = -40? to +85?, unless otherwise noted. typical values are at v cc = +5.0v, t a = +25?.) (note 5) note 5: ac parameters are guaranteed by design and characterization. note 6: input signal is a 1-0 pattern, 622mbps. note 7: pwd = [(width of wider pulse) - (width of narrower pulse)] / 2. t a = -40?, 2 23 - 1 prbs (notes 6, 7) (note 6) differential 20% to 80% conditions ? 3900 input resistance ps pulse-width distortion mv 3.2 minimum los assert input 15 80 % 20 data-output overshoot ps 250 data-output edge speed units min typ max parameter __________________________________________typical operating characteristics (MAX3761/max3762 ev kit, v cc = +5.0v, pecl outputs terminated with 50 ? to v cc - 2v, input is a 1-0 pattern, 622mbps, t a = +25?, unless otherwise noted.) 10 15 20 25 30 35 40 45 50 -40 -15 10 35 60 85 max3762 supply current vs. temperature MAX3761/62-01 ambient temperature (?) current (ma) v cc = 5.5v v cc = 5.0v v cc = 4.5v 10 100 1000 1 input signal (mvp-p) rssi voltage (v) 2.40 2.16 1.68 1.44 1.20 1.92 2.28 1.80 1.56 1.32 2.04 rssi vs. input amplitude and data pattern MAX3761/62-02 2 23 - 1 prbs pattern 1-0 pattern 2.40 1.20 -50 -40 -20 0 rssi vs. input power and frequency 1.44 2.16 MAX3761/62-03 input power (dbm) rssi voltage (v) -30 -10 -45 -25 -5 -35 -15 1.92 1.68 1.32 1.56 2.28 2.04 1.80 10mhz 500mhz 2 23 - 1 prbs, vth = 1.8v db 3.5 los hysteresis
100mv/ div 5 s/div los operation with squelching MAX3761/62-10 data in los+ out+ MAX3761/max3762 low-power, 622mbps limiting amplifiers with chatter-free power detect for lans 4 _______________________________________________________________________________________ 2.00 1.20 -40 -20 80 0 204060 rssi vs. temperature (622mbps 2 23 - 1 prbs) 1.36 1.84 MAX3761/62-04 ambient temperature ( c) rssi voltage (v) 1.68 1.52 1.28 1.44 1.92 1.76 1.60 v in = 50mvp-p v in = 16mvp-p v in = 4mvp-p 2.50 2.75 3.00 3.25 3.50 3.75 4.00 -40 -20 0 20406080100 los hysteresis vs. temperature (622mbps 2 23 - 1 prbs pattern) MAX3761/62-05 ambient temperature ( c) hysteresis (db) assert level set to approximately 2mvp-p assert level set to approximately 30mvp-p 3 4 5 6 7 8 -40 0 -20 20 40 60 80 100 los hysteresis vs. temperature (622mbps 1-0 pattern) MAX3761/62-06 ambient temperature ( c) hysteresis (db) assert level set to approximately 2mvp-p assert level set to approximately 30mvp-p -0.8 -1.8 -40 -20 0 20 40 60 80 data output levels (reference to v cc ) -1.6 -1.0 MAX3761/62-07 ambient temperature ( c) voltage (v) -1.2 -1.4 voh vol 1m 10 1 0.1 0.01 input signal (vp-p) differential output (mv) 1400 1280 1160 0.1m 1040 800 680 560 440 200 320 920 differential output vs. input amplitude MAX3761/62-08 0.01 0.1 1 10 0.001 input signal (vp-p) pulse-width distortion (ps) 50 40 20 10 0 30 pulse-width distortion (622mbps data rate) MAX3761/62-09 -40 c +85 c 100mv/ div 5 s/div data in los+ out+ los operation without squelching MAX3761/62-11 50mv/ div 500ps/div data output single-ended (2 23 - 1 prbs pattern) MAX3761/62-12 input = 4mvp-p t a = +85 c ____________________________typical operating characteristics (continued) (MAX3761/max3762 ev kit, v cc = +5.0v, pecl outputs terminated with 50 ? to v cc - 2v, input is a 1-0 pattern, 622mbps, t a = +25?, unless otherwise noted.)
MAX3761/max3762 low-power, 622mbps limiting amplifiers with chatter-free power detect for lans _______________________________________________________________________________________ 5 ____________________________typical operating characteristics (continued) (MAX3761/max3762 ev kit, v cc = +5.0v, pecl outputs terminated with 50 ? to v cc - 2v, input is a 1-0 pattern, 622mbps, t a = +25?, unless otherwise noted.) ______________________________________________________________pin description name function 1 filter sets the integration frequency of the power detector. impedance at this node is approximately 500 ? . 2 rssi received-signal-strength indicator. an analog dc voltage representing the input power. pin 50mv/ div 500ps/div data output single-ended (2 23 -1 prbs pattern) MAX3761/62-13 input = 2vp-p t a = +85 c 200mv/ div 200ps/div random jitter MAX3761/62-14 differential output (out+ - out-) input = 16mvp-p t a = +27 c 1-0 pattern 622mbps 10 4 10 5 10 6 10 3 frequency on power supply (hz) random jitter (ps rms) 10 8 4 2 6 random jitter vs. power-supply noise frequency MAX3761/62-15 differential output random jitter data input amplitude = 16mvp-p input amplitude power supply = 100mvp-p 3 en connect to v cc . 4, 17 v cc +5v power supply 5 vin+ positive input data 6 vin- negative input data 7 gnd supply ground 8 sub substrate. connect to ground. 9 czp sets input offset correction, low-frequency cutoff. 10 czn sets input offset correction, low-frequency cutoff. 11 inv negative input to op amp. used for programming the loss-of-signal threshold. 12 vth loss-of-signal threshold voltage 13 gndo ground power supply for output buffers 14 out- negative pecl data output 15 out+ positive pecl data output 16 vcco +5v power supply for output buffers 18 los- negative loss-of-power flag, ttl (MAX3761) or pecl (max3762) 19 los+ positive loss-of-power flag, ttl (MAX3761) or pecl (max3762) 20 disable disables the data outputs when high. ttl (MAX3761) or pecl (max3762).
MAX3761/max3762 low-power, 622mbps limiting amplifiers with chatter-free power detect for lans 6 _______________________________________________________________________________________ _______________detailed description figure 1 shows the functional diagram for the MAX3761/ max3762. the input signal is applied to vin+ and vin-. a chain of amplifier stages, each contributing approxi- mately 12.5db of gain, amplifies the input signal to pecl output voltage swings. a 4mvp-p input signal will cause the output to fully limit. received-signal-strength indicator (rssi) each amplifier stage contains a full-wave logarithmic detector (fwd). the full-wave detector outputs are summed at the filter pin and used to generate the received-signal-strength indication (rssi). the rssi output voltage is linearly proportional to the input power (in decibels), and is approximated by: where v in is the peak-to-peak input signal in millivolts. the rssi output is insensitive to fluctuations in temperature and supply voltage. the power detector functions as a broadband power meter that detects the total power of all signals present in the passband of approximately 750mhz. refer to the typical operating characteristics graphs show- ing rssi output versus input power and signal amplitude. the high-speed rssi signal is filtered with one external capacitor connected from filter to v cc . the imped- ance at the filter pin is approximately 500 ? . the filter capacitor (c filter ) must be connected to v cc for proper operation. input-offset correction the limiting amplifier provides approximately 60db of gain. an input dc offset of even 1mv reduces the power-detection circuit? accuracy and can cause the output to limit. a low-frequency feedback loop is inte- grated into the MAX3761/max3762 to remove input off- set. dc coupling the inputs is not recommended, as this prevents the dc-offset-correction circuitry from functioning properly. input offset is typically reduced to less than 100?. the capacitance between pins czp and czn, in parallel with a 10pf integrated capacitance, determines the off- set-correction circuit? time constant. the input imped- ance between czp and czn is approximately 800k ? . the offset correction circuitry requires an average data- input duty cycle of 50%. if the input data has a different average duty cycle, the output will have increased pulse-width distortion. v (v) = 1.13 + 0.457log (v ) rssi in limiter fwd limiter fwd limiter fwd filter ref inv vth r1 r2 gndo los+/los- v cc - 2v rssi 50 ? out+/out- disable vcco en czn c az czp sub gnd v cc vin+/vin- c in c filter v cc fwd = full-wave detector limiter fwd MAX3761/max3762 figure 1. functional diagram
loss-of-signal indicator the MAX3761/max3762 includes a loss-of-signal moni- tor with a programmable assert threshold and a hys- teresis comparator. internally, one comparator input is tied to the rssi output signal and the other is tied to the threshold-voltage (vth) pin, which provides a threshold for the los indication. an op amp referenced to an internal bandgap voltage (1.18v) is supplied for pro- gramming a supply-independent threshold voltage. only two external resistors are needed to program the los assert level. vth is programmable from 1.18v to 2.4v, providing adequate coverage of the rssi output? useful range. the op amp runs on very low supply cur- rent and provides an accurate, temperature-stable threshold, but can source only 20? of current. for proper operation, resistor r1 (see the typical operating circuit ) should have a value 100k ? . the input bias current at inv is < 50na. to ensure chatter-free los operation, the internal los comparator contains approximately 90mv of hysteresis. the rssi signal output has a slope of 25mv/db. therefore, the overall circuit hysteresis is approximately 3.6db[90mv / (25mv/db)]. the los assert threshold is 45mv below v th , while the los deassert threshold is 45mv above v th . output buffers the disable pin can be used to disable the data- output buffer. when disable is high, the differential output signal at out+ and out- is approximately zero. in the disabled state, the common-mode voltage of each output is approximately v cc - 0.8v. connecting disable to los+ implements a squelch function. when using the squelch function, the output signal is disabled whenever the input signal is too small to be reliably detected (as determined by the voltage at vth). use of the disable function is recommended at all times. the data outputs (out+ and out-) are implemented with emitter followers that have output impedance of approximately 2 ? . the max3762? pecl los outputs also are implemented with emitter followers that have output impedance of approximately 2 ? . the MAX3761 ttl los output buffers are open-collec- tor transistors with 6k ? internal pull-up resistors. __________________design procedure supply voltage the MAX3761/max3762 can be operated with a single +5v or -5v power supply. programming the los assert level first determine the receiver system? sensitivity in dbm either by estimating or from prototyping results. estimate the total gain of the preamplifier and photodi- ode, then use figure 3 to select resistor r2, placing the los assert 3db to 4db below the receiver sensitivity. alternatively, use the typical operating characteristics to select the v th value needed for los assert, then program v th with the following relation: v th = 1.18(1 + r2 / r1) select r1 100k ? . MAX3761/max3762 low-power, 622mbps limiting amplifiers with chatter-free power detect for lans _______________________________________________________________________________________ 7 v assert (min) v assert v deassert (max) v deassert v th 1.2v 45mv 25mv/db 45mv input signal amplitude rssi voltage 3.6db typical figure 2. loss-of-signal definitions 0 -38 -36 -28 -22 10 60 70 MAX3761/2-03 input signal (dbm) value of r2 (k ? ) -32 -34 -26 -30 -24 40 20 80 50 30 gain = 2000 gain = 6000 r1 = 100k ? gain = 4000 figure 3. using tia gain and photodiode responsivity to select los programming resistor gain is photodiode responsivity x transimpedance gain. extinction ratio of 10 is assumed.
MAX3761/max3762 capacitor selection a typical MAX3761/max3762 implementation requires four external capacitors. to select the capacitors, first determine the following parameters in the receiver sys- tem (see the applications information section for rec- ommendations in 622mbps atm and fibre channel 1063mbps systems): 1) the duration of the expected longest run of consec- utive bits in the data stream. for example, 72 con- secutive zeros in a 622mbps data stream have a duration of 116ns. 2) the maximum allowable data-dependent jitter. 3) the desired power-detector integration time con- stant [1 / (2 f int )]. 4) the transimpedance amplifier? maximum peak-to- peak output voltage. step 1. select the input ac-coupling capacitors (c in ). when using a limiting preamplifier with a highpass frequency response, select c in to provide a low- frequency cutoff (f c ) one decade lower than the preamplifier low-frequency cutoff. this causes nearly all data-dependent jitter (ddj) to be generated in the pre- amplifer circuit. for example, if the preamplifier? low- frequency cutoff is 150khz, then select c in to provide a 15khz low-frequency cutoff. select c in with the following equation: for differential input signals, use a capacitor equal to c in on both inputs (vin+ and vin-). for single-ended input signals, one capacitor should be tied to vin+ and another should decouple vin- to ground. when using a preamplifier without a highpass response, select c in to ensure that data-dependent jit- ter is acceptable. the following equation provides an estimate for c in : where: t l = duration of the longest run of consecutive bits with the same value (seconds); ddj = maximum allowable data-dependent jitter, peak-to-peak (seconds); bw = typical system bandwidth, normally 0.6 to 1.0 times the data rate (hertz). regardless of which method is used to select c in , the maximum los assert time can be estimated from the value of c in . the following equation estimates los time delay when the maximum-amplitude signal is instanta- neously removed from the input, and when the filter time constant is much faster than the input time con- stant (c filter < 0.4c in ): t los assert = 1950c in ln(v maxp-p / v assertp-p ) where v maxp-p is the maximum output of the preampli- fier, and v assertp-p is the input amplitude that causes los to assert. the equation describes the input capac- itors?discharge time, from maximum input to the los threshold into the 1950 ? , single-ended input resis- tance. step 2. select the offset-correction capacitor (c az ). to maintain stability, it is important to keep a one- decade separation between f c and the low-frequency cutoff associated with the dc-offset-correction circuit (f oc ). the input impedance between czp and czn is approximately 800k ? in parallel with 10pf. as a result, the low-frequency cutoff (f oc ) associated with the dc- offset-correction loop is computed as follows: where c az is an optional external capacitor between czp and czn. if c in is known, then: step 3. select the power-detect integration capacitor (c filter ). for 622mbps atm applications, maxim rec- ommends a filter frequency of 3mhz, which requires c filter = 100pf. the integration frequency can be selected lower to remove low-frequency noise, or to prevent unusual data sequences from asserting los. c filter = 1 / ( 2 500f int ) where f int is the integration frequency. c c pf az in ? 41 10 f = 1 2 800k oc ? cpf az + () 10 c - in l ? ()() ? ? ? ? ? ? ? ? t ddj bw 1950 1 05 ln . c = 1 2 f 1950 in c ? low-power, 622mbps limiting amplifiers with chatter-free power detect for lans 8 _______________________________________________________________________________________
__________applications information converting average optical power to signal amplitude many of the MAX3761/max3762? specifications relate to input-signal amplitude. when working with fiber optic receivers, the input is usually expressed in terms of average optical power and extinction ratio. the rela- tions given in table 1 are helpful for converting optical power to input signal when designing with the MAX3761/max3762. in an optical receiver, the input voltage to the limiting amplifier can be found by multiplying the relationship in table 1 with the photodiode responsivity (p) and tran- simpedance amplifier gain (g). optical hysteresis power and hysteresis are often expressed in decibels. by definition, decibels are always 10log (power). at the inputs to the MAX3761/max3762 limiting amplifier, the power is v in 2 /r. if a receiver? optical input power (x) increases by a factor of two, and the preamplifier is lin- ear, then the voltage input to the MAX3761/max3762 also increases by a factor of two. the optical power change is 10log(2x / x) = 10log(2) = +3db at the MAX3761/max3762, the voltage change is: in an optical receiver the db change at the MAX3761/ max3762 will always equal 2x the optical db change. the MAX3761/max3762? typical voltage hysteresis is 3.6db. this provides an optical hysteresis of 1.8db. input sensitivity the receiver? gain sensitivity defines the smallest signal input that results in fully limited pecl-compatible data outputs. smaller signals result in nonlimited outputs. the MAX3761/max3762? input sensitivity (s gain ) is 4mvp-p: s gain = 4mv optical gain sensitivity (in dbm) is: in a receiver with g = 6k ? , r e = 10, and = 0.8a/w, gain sensitivity is 510nw, or -32.9dbm. 622mbps atm component selection as an example, a preamplifier with a 150khz low- frequency cutoff and a 950mvp-p maximum output has the best performance with the following selections: c in = 5.6nf, so that f c = 15khz (one decade below the 150khz cutoff) c az = 150pf, so that f oc < 1.5khz (one decade below f c ) c filter = 100pf, so that the integration frequency equals 3mhz. these selections should provide data-dependent jitter less than 110ps p-p when the input consists of prbs data with no more than 72 consecutive bits. 10log s 2g x x gain r r e e + ? ? ? ? ? ? ? 1 1 1000 10 10 2 20 2 6 2 2 2 log log( ) log( ) 2v / r v / r in in () ===+ d b MAX3761/max3762 low-power, 622mbps limiting amplifiers with chatter-free power detect for lans _______________________________________________________________________________________ 9 table 1. optical-power relations* time p0 p1 p ave figure 4. optical-power relations symbol relation average power p ave parameter extinction ratio r e optical power of a ? p1 optical power of a ? p0 signal amplitude p in p = p0 + p1 ave () /2 r = 1 / p0 e p pp r r ave e e 12 1 = + pp r ave e 02 1 =+ () / ppp p r r in ave e e =? = ? () + 102 1 1 optical power * assuming a 50% average input data duty cycle (true for sonet/atm data).
MAX3761/max3762 for los assert at -35dbm, select r1 = 100k ? and r2 = 22k ? , which programs the los assert at input ? 3mv. with this selection, los assert time will typically be less than 85?. fibre channel component selection in fibre channel applications, the desired los assert time is typically 25? maximum, and data-dependent jitter is reduced by 8b10b coding techniques. the fol- lowing are recommended in a fibre channel system where preamp gain is 2000v/w, los assert is set for -24dbm (13mv MAX3761/max3762 input), and the maximum input to the MAX3761/max3762 is 1vp-p: c in = 3.3nf (to provide los assert in 25?) c az = 82pf (to provide f oc = 1/10 f c for stability) c filter = 100pf (for a 3mhz integration constant) r1 = 100k ? , r2 = 50k ? (to set los assert at -24dbm) pecl terminations the standard pecl termination (50 ? to v cc - 2v) is recommended for best performance and output char- acteristics. the data outputs operate at high speed, and should always drive transmission lines with 50 ? to 75 ? terminations. balanced termination is rec- ommended for all outputs. figure 5 shows an alternative method for terminating the data outputs. the technique provides approximate- ly 8ma dc bias current, with a 50 ? ac load, for the output termination. this technique is useful for viewing the output on an oscilloscope or changing the pecl reference voltage. the max3762? pecl los outputs are relatively slow and do not need 50 ? terminations (although they are capable of driving them). to reduce power, the max3762? los outputs can be terminated with 500 ? . figure 6 shows a typical operating circuit for the max3762. wire bonding for high current density and reliable operation, the MAX3761/max3762 use gold metalization. make con- nections to the dice with gold wire only, and use ball- bonding techniques (wedge bonding is not recommended). die-pad size is 4 mils square, with a 6 mil pitch. die thickness is 12 mils (0.3mm). layout techniques the MAX3761/max3762 are high-frequency, high- bandwidth circuits. to ensure stability, use good high- frequency layout techniques. filter voltage supplies, and keep ground connections short. use multiple vias where possible. use controlled-impedance transmis- sion lines to connect the MAX3761/max3762 data out- puts to other circuits. low-power, 622mbps limiting amplifiers with chatter-free power detect for lans 10 ______________________________________________________________________________________ 470 ? driving 50 ? to ground 470 ? 50 ? 50 ? out+ out- MAX3761 figure 5. alternative pecl termination
MAX3761/max3762 low-power, 622mbps limiting amplifiers with chatter-free power detect for lans ______________________________________________________________________________________ 11 czn out+ out- los- los+ disable sub gnd gndo 100pf 50 ? 500 ? czp r1 r2 +v cc vth inv max3762 c az 150pf 50 ? v cc - 2v v cc - 2v v cc - 2v v cc en rssi vcco vin+ 10nf 100pf c in 5.6nf c in 5.6nf +5v vin- filter c filter 500 ? ___________________chip topography _____________________________________typical operating circuits (continued) 0.063" (1.60mm) 0.059" (1.49mm) czp czn inv vth los- v cc vcco out+ out- gndo rssi filter disable los+ en v cc vin+ vin- gnd sub transistor count: 961 substrate connected to sub
maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 12 __________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 (408) 737-7600 2001 maxim integrated products printed usa is a registered trademark of maxim integrated products. MAX3761/max3762 low-power, 622mbps limiting amplifiers with chatter-free power detect for lans ________________________________________________________package information qsop.eps

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